As will be familiar to a person skilled in the art, semiconductor devices are conventionally packaged into the form of integrated circuits (an integrated circuit may also be referred to as an IC or “chip”). As shown schematically in FIG. 1A, an integrated circuit is a package comprising: a die 2 in which electronic components are formed, and surrounding packaging 1 including external pins 4 for connecting the die 2 to the external environment.
In some applications, as shown schematically in FIG. 1B, a plurality of dies 2 may be packaged onto the same chip and electrically connected to one another by conducting connections 5. An example of this is a multi-core processor, wherein a plurality of processors are each formed on a respective die 2, and packaged together on the same chip in an interconnected array or other arrangement so as to be able to communicate signals with one another via the connections 5.
However, due to certain packaging requirements, the need to provide conducting connections 5 between the multiple dies 2 can lead to additional and expensive manufacturing processing, increased chip size, and a more a complicated assembly process. Particularly, most dies 2 have a metal strengthening ring 3 formed close to their outer perimeter, sometimes referred to a “seal ring”. The need to arrange this ring 3 together with the interconnections 5, and ensure they are electrically isolated from one another, leads to these packaging issues. Similar packaging issues can be caused due to the connections between the die 2 and the pins 4, or connections between the die 2 and other components packaged on the same chip.
The seal ring 3 is now discussed in more detail. The structure of an integrated circuit is vulnerable to mechanical damage. For example, damage in the form of cracking can occur due to stresses during the wafer dicing process whereby the die is cut from a larger wafer comprising multiple dies formed on the same piece of silicon. Stresses can also occur due to thermal effects during the manufacturing process, or mechanical effects in the packaging, mounting or other processes, again potentially causing damage. Further, the structure may also be vulnerable to environmental damage such as damage due to impact or abrasion, chemical damage due to corrosion, and electrical damage due to static electricity (ESD).
Such cracking or other damage can lead to reliability issues. For example, cracking can lead to the ingress of moisture or other contamination, which reduces reliability of the chip.
In order to mitigate such issues, many ICs are manufactured having a strengthening ring 3 such as a seal ring. The seal ring 3 is formed in the die 2 around the outermost edge, and its primary role is to stop cracking of the chip. Any cracks that are created, e.g. during dicing, will follow a straight line and will be terminated and contained upon reaching the seal ring 3 at the outer edge of the die 2.
FIG. 1C shows a cross-sectional side view of the die 2 taken through the line C-C′ of FIG. 1A (it will be understood that similar dies 2 can be used in the multi-die package of FIG. 1B). The die 2 comprises a silicon substrate 6 in which p-n junction devices 7 are formed. A plurality of layers is laid over the substrate 6, comprising a plurality of alternate via layers 9 and interconnect layers 8 laid over one another. Each of these layers 8 and 9 comprises a layer of insulating dielectric material, in which are formed conducting interconnects 10 in the interconnect layers 8 and conducting vias 12 in the via layers 9. In accordance with the terminology used in the art, the interconnect layers 8 may be referred to as metal layers (although note that the vias 12 may also be made of metal).
The interconnects 10 form a network of conducting lines or runners in the horizontal plane (relative to the substrate); with the vias 12 providing vertical conducting connections between metal layers 8, as well as between the bottom-most metal layer 8E and the devices 7 of the substrate 6. The via layers 9 insulate the interconnects 10 of the different metal layers 8 from one another, except where it is desired that they should connect, at which points the vertical vias 12 are formed. The interconnects 10 and vias 12 together form electrical connections between the semiconductor devices 7, and may also be used to form other components such as capacitors or inductors, thus creating a functional electronic circuit. Some connections are shown in layers 8E, 9E, 8D and 9D of FIG. 1C, but it will of course be understood that connections may also be formed in other layers, that connections in the metal layers 8 may also be formed in the direction into the page, that a different number of layers may be provided, and generally that the diagram is a simplified, schematic example for illustrative purposes only. Some of the conductors 10p formed in the top-most metal layer 8A are used to connect to bond pads, to which are bonded wires connecting the circuit to the external pins 4 or connections 5 to other dies 2 on the same chip. Other packaging techniques could also be used, such as Flip Chip packaging whereby pads are formed on the bottom of the die.
The same layers 8 and 9 used to form electrical connections are also used to form the seal ring 3, by forming horizontally aligned layers of the ring from metal in both the metal layers 8 and via layers 9. Although the seal ring 3 is typically only a mechanical structure and does not form part of the electronic circuit, it can advantageously be formed at the same time as the electrical connections of the circuit as part of the same fabrication process. That is, from the point of view of the fabrication process there is no difference between the seal ring 3 and the electrical connections of the layers 8 and 9: the circuit designer simply patterns the seal ring 2 in the same manner as the electrical connections, so that it is etched and deposited by the fabrication equipment along with the electrical connections in the same manner. Thus the seal ring 3 can be included with minimal modification to the fabrication process.
A more detailed example of a seal ring structure can be found for example in U.S. Pat. No. 6,861,754 (Lin et al). Lin teaches that structural integrity is a particular issue in chips having low-k dielectrics and discloses a seal ring structure particularly suited for such chips.
It would be advantageous to be able to fabricate and package the seal ring 3 together with off-die connections such as 5 in a more efficient manner, in order to reduce the cost, size and/or manufacturing complexity of the chip.